Advances in semiconductor processing and logic design have permitted an increase in the amount of logic that may be present on integrated circuit devices. As a result, computer system configurations have evolved from a single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and/or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has grown, the power requirements for computing systems (from embedded systems to servers) have also escalated. Furthermore, software inefficiencies, and its requirements of hardware, have also caused an increase in computing device energy consumption. In fact, some studies indicate that computing devices consume a sizeable percentage of the entire electricity supply for a country, such as the United States of America. As a result, there is a vital need for energy efficiency and conservation associated with integrated circuits. These needs will increase as servers, desktop computers, notebooks, Ultrabooks™, tablets, mobile phones, processors, embedded systems, etc. become even more prevalent (from inclusion in the typical computer, automobiles, and televisions to biotechnology).
In advanced processor architectures, different intellectual property (IP) logic blocks may operate at different voltages/frequencies than a fabric. To couple different devices that operate at different frequencies, one or more buffers and credit circuitry may be provided at a boundary of the IP block and fabric. The depth of such buffer(s) can be defined by a worst case latency of credit activities. As buffer depth increases, the latency of data and credit transfer increases, causing an additional increase of buffer size, further increasing complexity, cost, power consumption and reducing performance.